Semiconductor devices are manufactured layer-by-layer using a variety of processes that may be considered to generally fall into four categories: forming layers, doping/annealing layers, patterning layers, and removing layers. For example, when forming an n-type field-effect transistor (NFET) in a device, it is typical to form a layer of polycrystalline silicon (also known as polysilicon) on a layer of silicon dioxide, which is in turn formed on a layer of mono-crystalline silicon. Then, n-type dopant ions, such as phosphorus, are introduced into portions of the polysilicon, such as with a particle beam. A polymer photo-resist layer is then formed on the doped polysilicon layer, and a pattern is optically projected onto the photo-resist layer (a technique known as lithography). Next, the photo-resist layer is developed such that portions of the photo-resist layer corresponding to the projected pattern are removed to expose portions of the underlying polysilicon. The exposed portions of polysilicon are etched away using the remaining photo-resist layer as a mask. The device may be carefully heated and cooled (a process known as annealing) to incorporate the dopants into the polycrystalline structure of the polysilicon. The result, when viewed from an overhead plan perspective, is a pattern of thin polysilicon lines extending across the surface of the device, which eventually are used as NFET gates and/or signal transmission lines. P-type field-effect transistor (PFET) gates are manufactured in a similar manner, except that p-type polysilicon doping is typically used. Other techniques may additionally or alternatively be used.
The thickness and pitch of the polycrystalline line is dictated by the technology, which is continuing to shrink as per Moore's Law. For example, for 45 nm technology, the minimum polycrystalline line width is about 40 nm with a pitch of about 140 nm. With feature sizes still shrinking, any variation of line width within a chip, commonly referred to as ACLV (across chip linewidth variation) becomes a major factor in lowering the clock speed of the chip. Among other factors, photo-resist thickness also contributes to the increase of ACLV during post etch. The thicker the photo-resist, the greater the ACLV. More particularly, the ACLV increases as the gate-to-resist thickness ratio decreases. It is therefore desirable to use the thinnest photo-resist layer possible. Typical gate-to-resist thickness ratios are 0.7 or less. On the other hand, during etching of the polysilicon, the photo-resist layer is also etched, albeit at a slower rate than the polysilicon. Thus, there are opposing factors between reducing the thickness of the photo-resist layer in order to decrease ACLV and providing a photo-resist layer that is sufficiently thick to withstand the etching process and protect the underlying polysilicon.